1) Field of the Invention
The Invention relates to a non-volatile memory cell with Twin MONOS structure, particularly aiming to high-speed application.
2) Description of the Related Art
Ishii et al. introduced the semiconductor memory element and its operation method in JP60200566 wherein two trap sites 51 and 52 exist in the insulator film underneath the gate (G) polysilicon layer 60 as shown in prior art FIG. 1A. The electron can be trapped in each trap site 51 and 52 as shown in FIG. 1A (1)-(4). Shown in each of the figures of FIG. 1A, 1B, and 1C are P-substrate 55 and n source and drain regions 53 and 54.
In FIG. 1B, the method to detect the data status (read) of the trap site 51 is shown. Gate 60 is set at high level (typically higher than 1V, hereinafter it is called “H” level) and select line SL 61 is set at low level (hereinafter it is called “L” level) e.g. ground level. And the data line DL 62 is set at “H” level. Vth over the channel (Ch) region 56 is high because the electrons exist at the trap site 51. Therefore, the MOSFET does not conduct the current even if gate 60 is set at “H” level and data line 62 is kept at “H” level. Depletion region 57 is illustrated.
In FIG. 1C, the method to detect the data status of the trap site 52 is shown. Gate 60 is set at “H” level and select line SL 64 is set at “L” level e.g. ground level. The data line DL 63 is set at “H” level. Ishii et al. found that in spite of electron storage at the drain edge, the current flows when an appropriate voltage is applied and the source side of state can be read as shown in Table 1. This is because the lateral length of electron storage is so small and the drain voltage of ˜1V can easily overcome the field by DIBL (Drain Induced Barrier Lowering) as pointed out later in U.S. Pat. No. 6,011,725 (Eitan et al.). Vth over the channel region 58 is low because the electrons do not exist at the trap site 52. Depletion region 59 is shown. Therefore, the MOSFET conducts the current and data line 63 voltage is lowered to “L” level. The DL set at “H” is always at the opposite side of the trap site read. The status wherein data line DL is “H” as shown in FIG. 1B is detected as data “1” and the status wherein data line DL is “L” as shown in FIG. 1C is detected as data “0”. Thus, one memory cell can store 2 bits of data. The data storage pattern in the memory cell and the read method in each pattern are shown in FIG. 1D. FIG. 1D illustrates the information detected in each of FIGS. 1A (1-4) where the source (S) and drain (D) are on the left (L) or right (R) sides of the figures.
Seiki Ogura et al. introduced Twin MONOS original cell structure and its device operation in U.S. Pat. Nos. 6,255,166, 6,399,441 and 6,388,293 (herein incorporated by reference in their entirety) wherein one memory cell can store two bits of data. The twin MONOS cell consists of a word gate as a select gate, a control gate pair on both sides of the word gate having an ONO memory element underneath, and a bit pair as source/drain diffusion on the other side of the control gate. The control voltages can be applied to the word gate and each of the control gates individually. The authors also provided two different array structures with fabrication methods; diffusion bit array in U.S. Pat. 6,248,633 and metal bit array in U.S. Pat. Nos. 6,469,935 and 6,531,350 (herein incorporated by reference in their entirety). In FIGS. 2A-B, the diffusion bit array structure is shown. FIG. 2A shows the cross sectional view of the diffusion bit array structure 65. The diffusion bit array shown in FIG. 2A consists of bit line 69 (bit lines BL<0> through BL<3>), control gate line 67 (control gates CG<0> through CG<3>) having ONO memory element 68 underneath along the bit line 69, and word gate 66 (word lines WL<0> and WL<1>) connecting select gates crossing the bit line. The insulation material with lower work function than oxide, such as Al2O3, HFO2, TiO2 or Ti2O5, can be utilized as the insulator in memory. Unit cell 70 is shown in FIGS. 2A and 2B.
The schematic diagram of the diffusion bit array is shown in FIG. 2B. It is convenient for high-density application. Metal bit array shown in FIGS. 3-4 consists of word line (WL) running parallel to control gate (CG) line and bit line (BL) crossing word line (WL) and control gate (CG). Numbered word lines (WL<0> through WL<N-1>), control gates (CG<0> through CG<N>). and bit lines (BL<0> through BL<A-1>), are shown. In FIG. 4, N is 5 and A is 5. FIG. 3 shows “2 cells per contact” type of a twin MONOS metal bit line memory array 1 wherein 2 storage sites (one of “hard bits” 201) share one bit line contact 202. FIG. 4 shows “4 cells per contact” type of a twin MONOS metal bit line memory array 2 wherein four storage sites (two of “hard bits” 203) share one bit line contact 204. For the memory element in a metal bit array, the insulation material with lower work function than oxide, such as Al2O3, HFO2, TiO2 or Ti2O5, can be utilized as the insulator in memory.